A general configuration employed nowadays for radio communication equipment such as an automobile telephone or a portable telephone, is one in which communication is switched to a channel specified by a base station when necessary, and therefore a high-speed channel switching performance is required for a synthesizer constituting a local oscillator.
An illustrative configuration of the conventional frequency synthesizer is shown in FIG. 1. This frequency synthesizer is used as a frequency source for an automobile telephone; and this automobile telephone has a battery power saving function when in a stand-by state.
In FIG. 1 indicates a reference oscillator for generating a highly stable reference frequency. Assume, in this example, that this oscillator oscillates at 12.8 MHz. 2 indicates a reference divider for dividing the reference frequency generated by the reference oscillator 1. In this case, the 12.8 MHz signal is divided into a 25 kHz reference signal f.sub.r. 3 indicates a phase comparator for performing comparison between a comparison signal f.sub.v from a comparison divider 8 described later and the reference signal f.sub.r from the reference divider 2, then delivering a phase difference signal (a lead signal or a lag signal) to a charge pump 4.
5 indicates a loop filter portion including a low-pass filter composed of resistors 151, 152 and a capacitor 153, the charging and discharging of this capacitor being controlled by the charge pump 4. An output signal from the loop filter portion 5 is fed, as a control voltage, to the input of a voltage-controlled oscillator 7 via a low-pass filter 6. The voltage-controlled oscillator 7 in this example is a circuit oscillating at a variable frequency of about 1.5 GHz; and an oscillation signal output therefrom is drawn as an output signal from the frequency synthesizer, and is fed to the input of the comparison divider 8 via a pre-scaler 70. The pre-scaler 70 is a circuit for dividing the oscillation frequency of about 1.5 GHz from the voltage-controlled oscillator 7 into a frequency of about 10 MHz, for example. The comparison divider 8 is a circuit for dividing the output signal from the pre-scaler 70 into the comparison signal f.sub.v of 25 kHz.
90 indicates a forced phase-locked loop. The forced phase-locked loop 90 is a circuit for effecting control so that the frequency synthesizer may quickly lock itself to a desired frequency when the frequency synthesizer is activated, that is, for example, when the power saving function is switched from ON to OFF. Specifically, the phase-locked loop is a circuit for forcing, by referring to the comparison signal f.sub.v of the comparison divider 8, phase lock-in in the reference divider 2 such that the phase of the reference signal f.sub.v of the reference divider 2 is in step with the phase of the comparison signal f.sub.v. Since, normally, the control voltage of the voltage-controlled oscillator 7 is maintained, when the power saving function is ON, at the same level as immediately before the power saving function is turned ON, the frequency of the comparison signal f.sub.v is maintained the same as the frequency of the reference signal f.sub.r even after the power saving function is OFF, but a phase difference is created between f.sub.r and f.sub.v. The forced phase-locked loop 90 reduces the time required for pull-in in the frequency synthesizer by forcing this phase difference to be zero.
In the above circuit, a circuit 20 marked off by a double line, that is, the circuit including the reference divider 2, the phase comparator 3, the charge pump 4, the comparison divider 8, and the forced phase-locked loop 90, is normally embodied by a single IC. Such IC circuit 20 is combined with the reference oscillator 1, the loop filter 5, the voltage-controlled oscillator, and the pre-scaler 70, to constitute the frequency synthesizer.
In this frequency synthesizer, the IC circuit 20 is provided with inputs of a clock CLK, data DATA, a strobe signal STB, and a power saving signal PS. The output frequency of the frequency synthesizer is adjusted by changing the dividing ratio of the reference divider 2 and the comparison divider 8 by means of this data DATA.
While it is true that the conventional frequency synthesizer achieves a high-speed frequency pull-in using the above-described forced phase-locked loop when recovering from the power saving mode, it should be noted that the time period, required for the phase-locked loop to frequency-lock or phase-lock with the desired frequency following a frequency switching, is determined by the time constant of the loop filter and the transfer function of each circuit. Since it needs a certain amount of time for the capacitor to be charged or discharged in the loop filter, the frequency switching takes time correspondingly. Therefore, the conventional circuit does not meet the demand for higher speed that is necessary, for example, in the aforementioned automobile telephone.